Monolithic ICs generally comprise vast number of active devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), or the like, and passive devices, such as resistors, etc., fabricated over a substrate. Current system on chip (SoC) technologies are focused on aggressively scaling the FET gate length (Lg) to provide performance and area scaling in accordance with Moore's Law.
Low leakage and/or high voltage transistors are important in SoC applications, but become more difficult with lateral scaling due, at least in part, to the architecture of high voltage transistors diverging from that of the high-performance logic transistor. Lateral scaling also reduces gate-contact spacing, which increases the peak electric field, further reducing a transistor's high voltage operating window. Also, lateral scaling exacerbates the hot carrier effect, which is a major limiter for high voltage transistors. To date, this incompatibility with advanced CMOS architecture and high voltage transistor architecture has motivated off-chip solutions, which are expensive and suffer performance limitations.
A device architecture enabling a non-planar transistor, such as a finFET, to be monolithically integrated with transistors able to have a gate dielectric with significantly greater equivalent oxide thickness (EOT) and a larger gate-drain spacing is advantageous for complex monolithic SOC IC designs employing power management circuitry, charge pump devices, RF power amplification circuitry, etc. that need transistors which can withstand higher breakdown voltages than needed for logic circuitry.